D-ID vs vLLM

vLLM tags frequently and most tags carry a single commit subject as their entire changelog. The window runs from the 0.25 rc series — Transformers-backend embedding scaling and CUDA graph capture, disaggregated prefill/decode KV-load lookahead under MTP speculative decoding, a flaky ARM ShortConv test — through the 0.26.1 and 0.27.0 tags, into the current 0.27.2rc0 carrying a confidence-scheduled verification scheme for speculative decoding. Hardware breadth is constant background work: TPU, ROCm, ARM and CUDA paths all appear.

Two things are being maintained at once. One is reach — keeping AMD, TPU and ARM honest, and keeping the Transformers modelling backend correct so new architectures run without bespoke kernels. The other is speculative decoding, which keeps producing work at its seams: first the interaction with disaggregated prefill/decode, now the verification schedule itself. The rc tags carry the interesting commits and the stable tags mostly ratify them, so reading only the stable releases understates what is moving.

The confidence-scheduled verification work should surface in a 0.27.2 stable tag on the usual short rc-to-release gap. Whether it becomes a default or stays an opt-in scheduler is not answerable from a commit subject.